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integrated circuit systems, inc. ics94201 0428b- 11/28/05 pin configuration recommended application: 810/810e and solano (815) type chipset output features: ? 2 - cpus @ 2.5v 13 - sdram @ 3.3v 3 - 3v66 @ 3.3v 8 - pci @3.3v 1 - 24/48mhz@ 3.3v 1 - 48mhz @ 3.3v fixed 1 - ref @3.3v, 14.318mhz features: programmable ouput frequency. programmable ouput rise/fall time for pci and sdram clocks. programmable 3v66 to pci skew. spread spectrum for emi control with programmable spread percentage. watchdog timer technology to reset system if over-clocking causes malfunction. support power management through pd#. uses external 14.318mhz crystal. fs pins for frequency select key specifications: cpu output jitter: <250ps ioapic output jitter: <500ps 48mhz, 3v66, pci output jitter: <500ps cpu output skew: <175ps pci output skew: <500ps 3v66 output skew <175ps for group skew timing, please refer to the group timing relationship table. programmable system frequency generator for p ii / iii ? 56-pin 300 mil ssop 1. these pins will have 1.5 to 2x drive strength. * 120k ohm pull-up to vdd on indicated inputs. pll2 pll1 spread spectrum 48mhz 24_48mhz cpuclk [1:0] 2 12 8 3 sdram [11:0] ioapic pciclk [7:0] sdram_f 3v66 [2:0] x1 x2 xtal osc cpu divder sdram divder ioapic divder pci divder 3v66 divder fs[4:0] pd# sel24_48# s data sclk control logic config. reg. / 2 ref0 block diagram vddref x1 x2 gndref gnd3v66 3v66-1 3v66-2 vdd3v66 vddpci *(fs0)pciclk0 *(fs1)pciclk1 *(sel24_48#)pciclk2 gndpci pciclk3 pciclk4 pciclk5 vddpci pciclk6 pciclk7 gndpci pd# sclk s data vddsdr sdram11 sdram10 gndsdr 3v66-0 1 1 1 ref0(fs4)* vddlapic ioapic vddlcpu cpuclk0 cpuclk1 gndlcpu gndsdr sdram0 sdram1 sdram2 vddsdr sdram3 sdram4 sdram5 gndsdr sdram6 sdram7 sdram_f vddsdr gnd48 24_48mhz(fs2)* 48mhz(fs3)* vdd48 vddsdr sdram8 sdram9 gndsdr 1 1 ics94201 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics94201 0428b - 11/28/05 general description pin configuration the ics94201 is a single chip clock solution for desktop designs using the 810/810e and solano style chipset. it provides all necessary clock signals for such a system. the ics94201 belongs to ics new generation of programmable system clock generators. it employs serial programming i 2 c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to outpu t skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. spread spectrum typically reduces system emi by 7db to 8db. this simplifies emi qualification without resorting to board design iterations or costly shielding. n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d , 5 2 , 8 1 , 0 1 , 9 , 1 5 4 , 7 3 , 3 3 , 2 3 d d vr w py l p p u s r e w o p v 3 . 3 21 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 32 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 1 2 , 4 1 , 5 , 4 , 6 3 , 9 2 , 8 2 9 4 , 1 4 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 6 , 7 , 8] 0 : 2 [ 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 1 1 0 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , t u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 2 1 1 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 3 1 # 8 4 _ 4 2 _ l e sn i. t u p t u o t c e l e s o t t u p n i c i g o l 2 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , t u p t u o k c o l c i c p v 3 . 3 , 7 1 , 9 1 , 0 2 5 1 , 6 1 ] 3 : 7 [ k l c i c pt u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 2 2# d pn i a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c . s m 3 n a h t 3 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 4 2a t a d st u oi r o f t u p n i a t a d 2 . t u p n i l a i r e s c 4 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 8 4t u ob s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 5 3 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 8 4 _ 4 2t u o. z h m 4 2 s i t l u a f e d , 3 1 n i p h g u o r h t e l b a t c e l e s , t u p t u o z h m 8 4 _ 4 2 v 3 . 3 8 3f _ m a r d st u oi h g u o r h t f f o d e n r u t e b n a c t u p t u o m a r d s v 3 . 3 2 c , 4 4 , 6 4 , 7 4 , 8 4 , 9 3 , 0 4 , 2 4 , 3 4 6 2 , 7 2 , 0 3 , 1 3 ] 0 : 1 1 [ m a r d st u oi h g u o r h t f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . t u p t u o v 3 . 3 2 c 0 5l d n gr w pc i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 2 5 , 1 5] 0 : 1 [ k l c u p ct u o. s n i p s f m o r f d e v i r e d y c n e u q e r f t u p t u o . t u p t u o k c o l c s u b t s o h v 5 . 2 5 5 , 3 5l d d vr w pc i p a o i , u p c r o f y l p p y u s r e w o p v 5 . 2 4 5c i p a o it u o. z h m 7 6 . 6 1 t a g n i n n u r s t u p t u o k c o l c v 5 . 2 6 5 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 0 f e r 1 t u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3
3 ics94201 0428b - 11/28/05 general i 2 c serial interface information for the ics94201 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending byte 0 through byte 28 (see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends byte 0 through byte 6 (default) ? ics clock sends byte 0 through byte x (if x (h) was written to byte 6). ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 26 ack byte 27 ack byte 28 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 1a h has been written to b6 byte26 ack if 1b h has been written to b6 byte 27 ack if 1c h has been written to b6 byte 28 ack stop bit how to read: *see notes on the following page .
4 ics94201 0428b - 11/28/05 notes: 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to read back is defined by writing to byte 6. 2. when writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8-bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-5 active / inactive output control registers. see individual byte description byte count read back register 6 w riting to this register will configure byte count and how many byte will be read back. do not write 00 h to this byte. 06 h latched inputs read back register 7 the inverse of the latched inputs level could be read back from this register. see individual byte description w atchdog control registers 8 bit[6:0] w atchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 8 bit[7] this bit selects whether the output frequency is controled by hardware/byte 0 configurations or byte 14&15 programming. 0 w atchdog timer count register 9 w riting to this register will configure the number of seconds for the watchdog timer to reset. ff h ics reserved register 10 this is an unused register. w riting to this register will not affect device functionality. 00 h device id, vendor id & revision id registers 11-12 byte 11 bit[3:0] is ics vendor id - 0001. other bits in these 2 registers designate device revision id of this part. see individual byte description ics reserved register 13 don't write into this register, writing 1's will cause malfunction. 00 h vco frequency control registers 14-15 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depend on hardware/byte 0 configuration spread spectrum control registers 16-17 these registers control the spread percentage amount. depend on hardware/byte 0 configuration output dividers control registers 18-20 changing bits in these registers result in frequency divider ratio changes. incorrect configuration of group output divider ratio can cause system malfunction. depend on hardware/byte 0 configuration group skews control registers 21-23 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 24 these registers will control the group rise and fall time. see individual byte description brief i 2 c registers description for ics94201 programmable system frequency generator
5 ics94201 0428b - 11/28/05 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b7 t i b6 t i b5 t i b4 t i b f e r / o c v r e d i v i d o c v z h m / o c v u p c k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m c i p a o i z h m 1 e t o n 4 s f3 s f2 s f1 s f0 s f 00000 8 1 / 1 0 52 5 . 8 9 363 4 . 6 65 6 . 9 93 4 . 6 61 2 . 3 31 6 . 6 1 00001 4 1 / 2 5 30 0 . 0 6 360 0 . 0 60 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1 00010 8 1 / 4 0 51 9 . 0 0 460 8 . 6 60 2 . 0 0 10 8 . 6 60 4 . 3 30 7 . 6 1 00011 1 1 / 5 1 32 0 . 0 1 463 3 . 8 60 5 . 2 0 13 3 . 8 67 1 . 4 38 0 . 7 1 00100 5 1 / 0 4 40 0 . 0 2 460 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 00101 4 1 / 0 4 40 0 . 0 5 460 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 00110 5 1 / 3 0 54 1 . 0 8 460 0 . 0 80 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2 00111 9 / 3 1 35 9 . 7 9 460 0 . 3 80 5 . 4 2 10 0 . 3 80 5 . 1 45 7 . 0 2 01000 7 3 / 5 1 59 2 . 9 9 125 6 . 9 95 6 . 9 93 4 . 6 61 2 . 3 31 6 . 6 1 01001 5 3 / 0 4 49 2 . 0 8 120 0 . 0 90 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1 01010 7 3 / 8 1 55 4 . 0 0 22 3 2 . 0 0 13 2 . 0 0 14 8 . 6 61 4 . 3 30 7 . 6 1 01011 1 3 / 6 4 40 0 . 6 0 22 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1 01100 3 3 / 4 8 40 0 . 0 1 22 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 01101 3 3 / 7 0 58 9 . 9 1 22 0 0 . 0 1 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 1 01110 2 3 / 4 1 59 9 . 9 2 22 0 0 . 5 1 10 0 . 5 1 17 6 . 6 73 3 . 8 37 1 . 9 1 01111 6 1 / 7 4 41 0 . 0 0 42 0 0 . 0 0 20 0 . 0 0 23 3 . 3 3 16 6 . 6 63 3 . 3 3 10000 8 1 / 1 0 52 5 . 8 9 33 6 8 . 2 3 16 8 . 2 3 13 4 . 6 61 2 . 3 31 6 . 6 1 1000 1 3 1 / 4 5 43 0 . 0 0 53 7 6 . 6 6 17 6 . 6 6 14 3 . 3 87 6 . 1 43 8 . 0 2 100 10 8 1 / 4 0 51 9 . 0 0 43 4 6 . 3 3 14 6 . 3 3 12 8 . 6 61 4 . 3 30 7 . 6 1 100 11 7 1 / 8 8 42 0 . 1 1 43 0 0 . 7 3 10 0 . 7 3 10 5 . 8 65 2 . 4 33 1 . 7 1 10 100 5 1 / 0 4 40 0 . 0 2 43 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1 10 10 1 3 1 / 5 9 35 0 . 5 3 43 0 0 . 5 4 10 0 . 5 4 10 5 . 2 75 2 . 6 33 1 . 8 1 10 110 4 1 / 0 4 40 0 . 0 5 43 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 35 7 . 8 1 10 111 5 1 / 3 0 54 1 . 0 8 43 0 0 . 0 6 10 0 . 0 6 10 0 . 0 80 0 . 0 40 0 . 0 2 11000 8 1 / 1 0 52 5 . 8 9 33 6 8 . 2 3 15 6 . 9 93 9 . 6 61 2 . 3 31 6 . 6 1 11001 3 1 / 4 5 43 0 . 0 0 53 7 6 . 6 6 10 0 . 5 2 14 3 . 3 87 6 . 1 43 8 . 0 2 11010 8 1 / 4 0 51 9 . 0 0 43 4 6 . 3 3 13 2 . 0 0 12 8 . 6 61 4 . 3 37 . 6 1 11011 7 1 / 8 8 42 0 . 1 1 43 0 0 . 7 3 15 7 . 2 0 10 5 . 8 65 2 . 4 33 1 . 7 1 11100 5 1 / 0 4 40 0 . 0 2 43 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 11101 3 1 / 5 9 35 0 . 5 3 43 0 0 . 5 4 15 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 1 11110 4 1 / 0 4 40 0 . 0 5 43 0 0 . 0 5 10 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 11111 5 1 / 3 0 54 1 . 0 8 43 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 3 . 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
6 ics94201 0428b - 11/28/05 byte 1: output control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default byte 3: output control register (1 = enable, 0 = disable) byte 2: output control register (1 = enable, 0 = disable) byte 4: output control register (1 = enable, 0 = disable) byte 5: output control register (1 = enable, 0 = disable) byte 6: byte count read back register note: writing to this register will configure byte count and how many bytes will be read back, default is 6 bytes. t i b# n i pd w pn o i t p i r c s e d 7 t i b9 31 7 m a r d s 6 t i b0 41 6 m a r d s 5 t i b2 41 5 m a r d s 4 t i b3 41 4 m a r d s 3 t i b4 41 3 m a r d s 2 t i b6 41 2 m a r d s 1 t i b7 41 1 m a r d s 0 t i b8 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b81 2 _ 6 6 v 3 6 t i b61 0 _ 6 6 v 3 5 t i b71 1 _ 6 6 v 3 4 t i b-x# 4 s f 3 t i b4 51 c i p a o i 2 t i b-x# 1 s f 1 t i b1 51 1 k l c u p c 0 t i b2 51 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b6 21 1 1 m a r d s 2 t i b7 21 0 1 m a r d s 1 t i b0 31 9 m a r d s 0 t i b1 31 8 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b9 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b5 11 3 k l c i c p 2 t i b3 11 2 k l c i c p 1 t i b2 11 1 k l c i c p 0 t i b1 11 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 3 s f 6 t i b-x# 0 s f 5 t i b-x# 2 s f 4 t i b5 31 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b4 31 z h m 8 4 1 t i b-1 ) d e v r e s e r ( 0 t i b8 31 f _ m a r d s
7 ics94201 0428b - 11/28/05 byte 7: latch inputs readback register byte 9: watchdog timer count register byte 8: vco control selection bit & watchdog timer control register byte 10: ics reserved register byte 11: vender id & device id register byte 12: revision id register note: fs values in bit [0:4] will correspond to byte 0 fs values. default safe frequency is same as 00000 entry in byte0. note: this is an unused register. writing to this register will not affect device performance or functionality. note: ics vendor id is 0001 as in number 1 in frequency generation. notes: 1. pwd = power on default t i bd w pn o i t p i r c s e d 7 t i b0 q e r f 5 1 & 4 1 b = 1 / q e r f 0 b / w h = 0 6 t i b0 e l b a n e = 1 / e l b a s i d = 0 e l b a n e d w 5 t i b0 m r a l a = 1 / l a m r o n = 0 s u t a t s d w 4 t i b0 4 s f , y c n e u q e r f e f a s d w 3 t i b0 3 s f , y c n e u q e r f e f a s d w 2 t i b0 2 s f , y c n e u q e r f e f a s d w 1 t i b0 1 s f , y c n e u q e r f e f a s d w 0 t i b0 0 s f , y c n e u q e r f e f a s d w t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 ) d e v r e s e r ( 5 t i b0 ) d e v r e s e r ( 4 t i b0 ) d e v r e s e r ( 3 t i b0 ) d e v r e s e r ( 2 t i b0 ) d e v r e s e r ( 1 t i b0 ) d e v r e s e r ( 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i bx d i n o i s i v e r 6 t i bx d i n o i s i v e r 5 t i bx d i n o i s i v e r 4 t i bx d i n o i s i v e r 3 t i bx d i e c i v e d 2 t i bx d i e c i v e d 1 t i bx d i e c i v e d 0 t i bx d i e c i v e d t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 ) d e v r e s e r ( 5 t i b0 ) d e v r e s e r ( 4 t i bx# 4 s f 3 t i bx# 3 s f 2 t i bx# 2 s f 1 t i bx# 1 s f 0 t i bx# 0 s f t i bd w pn o i t p i r c s e d 7 t i b1 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t s m 2 r o s m 0 8 5 o t d n o p s e r r o c s t i b 8 e h t ) 4 t i b 3 1 e t y b y b e l b a t c e l e s ( t i e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t t e s e r d n a e d o m m r a l a o t s e o g t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f 8 4 1 = s m 0 8 5 x 6 5 2 s i p u r e w o p t a s d n o c e s 6 t i b1 5 t i b1 4 t i b1 3 t i b1 2 t i b1 1 t i b1 0 t i b1 t i bd w pn o i t p i r c s e d 7 t i bx d i e c i v e d 6 t i bx d i e c i v e d 5 t i bx d i e c i v e d 4 t i bx d i e c i v e d 3 t i b0 d i r o d n e v 2 t i b0 d i r o d n e v 1 t i b0 d i r o d n e v 0 t i b1 d i r o d n e v note: device id and revision id values will be based on individual device and its revision.
8 ics94201 0428b - 11/28/05 byte 13: ics reserved register byte 15: vco frequency control register note: the decimal representation of these 9 bits (byte 15 bit [7:0] & byte 14 bit [7] ) + 8 is equal to the vco divider value. for example if vco divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 15 bit & byte 14 bit 7. note: don't write a '1' into this register, it will cause malfunction. byte 14: vco frequency control register note: the decimal representation of these 7 bits (byte 14 [6:0]) + 2 is equal to the ref divider value . to program the vco frequency for over-clocking. 0. before trying to program our clock manually, consider using ics provided software utilities for easy programming. 1. select the frequency you want to over-clock from with the desired gear ratio (i.e. cpu:sdram:3v66:pci ratio) by writing to byte 0, or using initial hardware power up frequency. 2. write 0001, 1001 (19 h ) to byte 6 for readback of 25 bytes (byte 0-24). 3. read back byte 16-24 and copy values in these registers. 4. re-initialize the write sequence. 5. write a '1' to byte 8 bit 7 indicating you want to use byte 14 and 15 to control the vco frequency. 6. write to byte 14 & 15 with the desired vco & ref divider values. 7. write to byte 16 to 24 with the values you copy from step 3. this maintains the output divider mux controls the same gear r atio. 8. the above procedure is only needed when changing the vco for the 1st pass. if vco frequency needs to be changed again, user only needs to write to byte 14 and 15 unless the system is to reboot. vco programming constrains vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 useful formula vco frequency = 14.31818 x vco/ref divider value phase detector stabiliy = 14.038 x (vco divider value) -0.5 t i bd w pn o i t p i r c s e d 7 t i bx 8 t i b r e d i v i d o c v 6 t i bx 7 t i b r e d i v i d o c v 5 t i bx 6 t i b r e d i v i d o c v 4 t i bx 5 t i b r e d i v i d o c v 3 t i bx 4 t i b r e d i v i d o c v 2 t i bx 3 t i b r e d i v i d o c v 1 t i bx 2 t i b r e d i v i d o c v 0 t i bx 1 t i b r e d i v i d o c v t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 ) d e v r e s e r ( 5 t i b0 ) d e v r e s e r ( 4 t i b0 t c e l e s e s a b r e m i t 0 w s m 0 8 5 = 0 s m 2 = 1 3 t i b0 ) d e v r e s e r ( 2 t i b0 ) d e v r e s e r ( 1 t i b0 ) d e v r e s e r ( 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i bx 0 t i b r e d i v i d o c v 6 t i bx 6 t i b r e d i v i d f e r 5 t i bx 5 t i b r e d i v i d f e r 4 t i bx 4 t i b r e d i v i d f e r 3 t i bx 3 t i b r e d i v i d f e r 2 t i bx 2 t i b r e d i v i d f e r 1 t i bx 1 t i b r e d i v i d f e r 0 t i bx 0 t i b r e d i v i d f e r
9 ics94201 0428b - 11/28/05 byte 16: spread sectrum control register byte 17: spread spectrum control register note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. byte 18: output dividers control register byte 19: output dividers control register note: changing bits in these registers results in frequency divider ratio changes. incorrect configuration of group gear ratio can cause system malfunction. note: changing bits in these registers results in frequency divider ratio changes. incorrect configuration of group gear ratio can cause system malfunction. notes: 1. pwd = power on default 2. the power on default for byte 16-20 depends on the harware (latch inputs fs[0:4]) or iic (byte 0 bit [1:7]) setting. be sur e to read back and re-write the values of these 5 registers when vco frequency change is desired for the first pass. t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 6 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 5 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 4 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 3 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 0 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i bx 5 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 4 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 3 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 2 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 1 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 0 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 9 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 8 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b m u r t c e p s d a e r p s 6 t i bx 6 t i b m u r t c e p s d a e r p s 5 t i bx 5 t i b m u r t c e p s d a e r p s 4 t i bx 4 t i b m u r t c e p s d a e r p s 3 t i bx 3 t i b m u r t c e p s d a e r p s 2 t i bx 2 t i b m u r t c e p s d a e r p s 1 t i bx 1 t i b m u r t c e p s d a e r p s 0 t i bx 0 t i b m u r t c e p s d a e r p s t i bd w pn o i t p i r c s e d 7 t i bx 6 2 t i b l o r t n o c r e d i v i d 6 t i b0 5 2 t i b l o r t n o c r e d i v i d 5 t i bx 4 2 t i b l o r t n o c r e d i v i d 4 t i bx 2 1 t i b m u r t c e p s d a e r p s 3 t i bx 1 1 t i b m u r t c e p s d a e r p s 2 t i bx 0 1 t i b m u r t c e p s d a e r p s 1 t i bx 9 t i b m u r t c e p s d a e r p s 0 t i bx 8 t i b m u r t c e p s d a e r p s note: 1. user needs to ensure step 3 & 7 is carried out. systems with the wrong spread percentage and/or group to group divider rati o programmed into bytes 16-20 could be unstable. step 3 & 7 assure the correct spread and gear ratio. 2. if vco, ref divider values or phase detector stability are out of range, the device may fail to function correctly. 3. follow min and max vco frequency range provided. internal pll could be unstable if vco frequency is too fast or too slow. use 14.31818mhz x vco/ref divider values to calculate the vco frequency (mhz). 4. users can also utilize software utility provided to program the vco frequency from ics application engineering. 5. spread percent needs to be calculated based on vco frequency, spread modulation frequency and spread amount desired. see application note for software support.
10 ics94201 0428b - 11/28/05 byte 21: ics reserved register byte 23: group skew control register byte 22: group skew control register note: default 3v66 to pci skew is 2.5ns bit [7:4]=1001. each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all pci clocks. byte 24: output rise/fall time select register note: this is an unused register. writing to this register will not affect device performance or functionality. byte 20: output dividers control register note: changing bits in these registers results in frequency divider ratio changes. incorrect configuration of group gear ratio can cause system malfunction. notes: 1. pwd = power on default 2. the power on default for byte 16-20 depends on the hardware (latch inputs fs[0:4]) or i 2 c (byte 0 bit [1:7]) setting. be sure to read back and re-write the values of these 5 registers when vco frequency change is desired for the first pass. 3. if byte 8 bit 7 is driven to "1" meaning programming is intended, byte 21-24 will lose their default power up value. note: default 3v66 to ioapic skew is 2.5ns bit [3:0]=0111. each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all ioapic clocks. t i bd w pn o i t p i r c s e d 7 t i bx 3 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 2 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 1 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 0 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 9 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 8 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 7 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 6 1 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i b 0) d e v r e s e r ( 6 t i b 0) d e v r e s e r ( 5 t i b 0) d e v r e s e r ( 4 t i b 0) d e v r e s e r ( 3 t i b 0) d e v r e s e r ( 2 t i b 0) d e v r e s e r ( 1 t i b 0) d e v r e s e r ( 0 t i b 0) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i b1 3 t i b w e k s i c p o t 6 6 v 3 6 t i b0 2 t i b w e k s i c p o t 6 6 v 3 5 t i b0 1 t i b w e k s i c p o t 6 6 v 3 4 t i b1 0 t i b w e k s i c p o t 6 6 v 3 3 t i b0 ) d e v r e s e r ( 2 t i b0 ) d e v r e s e r ( 1 t i b0 ) d e v r e s e r ( 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 k a e w = 1 , l a m r o n = 0 f e r 5 t i b0 k a e w = 1 , l a m r o n = 0 z h m 8 4 , 4 2 4 t i b0 ) d e v r e s e r ( 3 t i b0 k a e w = 1 , l a m r o n = 0 i c p 2 t i b0 k a e w = 1 , l a m r o n = 0 6 6 v 3 1 t i b0 k a e w = 1 , l a m r o n = 0 m a r d s 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i b 0) d e v r e s e r ( 6 t i b 0) d e v r e s e r ( 5 t i b 0) d e v r e s e r ( 4 t i b 0) d e v r e s e r ( 3 t i b 03 t i b w e k s c i p a o i o t 6 6 v 3 2 t i b 12 t i b w e k s c i p a o i o t 6 6 v 3 1 t i b 11 t i b w e k s c i p a o i o t 6 6 v 3 0 t i b 10 t i b w e k s c i p a o i o t 6 6 v 3
11 ics94201 0428b - 11/28/05 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115c group timing relationship table 1 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 i il2 v in = 0 v; inputs with pull-up resistors -200 c l = max cap loads; cpu=66-133 mhz , sdram=100 mhz 334 350 cpu=133 mhz, sdram=133 mhz 465 500 i dd2.5op c l = max cap loads; 20 70 powerdown current i dd3.3pd c l = 0 pf; input address to vdd or gnd 280 600 a input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 input capacitance 1 input low current a i dd3.3op operating supply current ma offset tolerance offset tolerance offset tolerance offset tolerance cpu to sdram 2.5 ns 500 ps 5.0 ns 500 ps 0.0 ns 500 ps 3.75 ns 500 ps cpu to 3v66 7.5 ns 500 ps 5.0 ns 500 ps 0.0 ns 500 ps 0.0 ns 500 ps sdram to 3v66 0.0 ns 500 ps 0.0 ns 500 ps 0.0 ns 500 ps 3.75 ns 500 ps 3v66 to pci 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps 1.5-3.5ns 500 ps pci to ioapic 0.0 ns 1.0 ns 0.0 ns 1.0 ns 0.0 ns 1.0 ns 0.0 ns 1.0 ns usb & dot asynch n/a asynch n/a asynch n/a asynch n/a 1 guaranteed by design, not 100% tested in production. group sdram 100 mhz s dram 100 mhz s dram 100 mhz s dram 133 mhz cpu 66 mhz cpu 100 mhz cpu 133 mhz cpu 133 mhz
12 ics94201 0428b - 11/28/05 electrical characteristics - cpu t a = 0 - 70o c; v ddl = 2.5 v +/-5%; c l = 10 - 20 p f (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp2b vo=v dd *(0.5) 13.5 15 45 ? output impedance 1 r dsn2b vo=v dd *(0.5) 13.5 16.5 45 ? output high voltage v oh2b i oh = -1 ma 2 2.48 v output low voltage v ol2b i ol = 1 ma 0.04 0.4 v v oh@min = 1 v -60 -27 v oh@max = 2.375v -27 -7 v ol@min = 1.2 v 27 63 v ol@max =0.3v 20 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 50 55 % skew 1 t sk2b v t = 1.25 v 30 175 ps v t = 1.25 v, cpu 66, sdram 100 300 350 cpu 100, sdram 100 240 250 cpu 133, sdram 100 400 500 cpu 133, sdram 133 300 350 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc2b ps ma ma output high current i oh2b output low current i ol2b electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp1 v o = v dd *(0.5) 12 55 ? output impedance 1 r dsn1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 v oh @ max = 3.135 v -33 v ol @ min = 1.95 v 30 v ol @ max = 0.4 v 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 0.9 1.6 ns duty cycle 1 d t1 v t = 1.5 v 45 49 55 % skew 1 t sk1 v t = 1.5 v 35 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 220 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1
13 ics94201 0428b - 11/28/05 electrical characteristics - ioapic t a = 0 - 70o c; v ddl = 2.5 v +/-5%; c l = 10 - 20 p f (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp4b vo=v dd *(0.5) 93 ? output impedance 1 r dsn4b vo=v dd *(0.5) 930 ? output high voltage v oh4b i oh = -5.5 ma 2 v output low voltage v ol4b i ol = 9 ma 0.4 v v oh @ min = 1.4 v -21 v oh@max = 2.5v -36 v ol@min = 1.0 v 36 v ol@max =0.2v 31 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 50 55 % jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 240 500 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh4b output low current i ol4b electrical characteristics - sdram t a = 0 - 70o c; v dd = 3.3 v +/-5%, c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp3 vo=v dd *(0.5) 10 24 ? output impedance 1 r dsn3 vo=v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh @ min = 2 v -46 v oh@max = 3.135v -54 v ol@min = 1 v 54 v ol@max =0.4v 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 0.9 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 0.8 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 49 55 % skew 1 t sk3 v t = 1.5 v 100 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc3 v t = 1.5 v 350 500 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh3 output low current i ol3
14 ics94201 0428b - 11/28/05 electrical characteristics - pci t a = 0 - 70o c; v dd = 3.3 v +/-5%, c l = 40 p f for pci0-1, c l = 10 - 30 p f for other pcis (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp1 vo=v dd *(0.5) 12 55 ? output impedance 1 r dsn1 vo=v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1 v -33 v oh@max = 3.135v -33 v ol@min = 1.95 v 30 v ol@max =0.4v 38 v ol = 0.4 v, v oh = 2.4 v, pci0-3 1.8 2 pci3-7 2.2 2.5 v ol = 2.4 v, v oh = 0.4 v, pci0-3 1.8 2 pci3-7 2.3 2.5 duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew 1 t sk1 v t = 1.5 v 150 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 200 500 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh1 output low current i ol1 t r1 rise time 1 fall time 1 t f1 ns ns 0.5 0.5 electrical characteristics - ref, 24_48mhz, 48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v dd *(0.5) 20 60 ? output impedance 1 r dsn5 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.4 v v oh @ min = 1.0 v -23 v oh @ max = 3.135 v -29 v ol @ min = 1.95 v 29 v ol @ max = 0.4 v 27 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 2 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % v t = 1.5 v, fixed clocks 200 500 v t = 1.5 v, ref clocks 2300 3000 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc5 ps output high current i oh5 ma output low current i ol5 ma
15 ics94201 0428b - 11/28/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics94201 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5- bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
16 ics94201 0428b - 11/28/05 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz
17 ics94201 0428b - 11/28/05 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
18 ics94201 0428b - 11/28/05 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c0.130.25.005.010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h0.380.64.015.025 l0.501.02.020.040 n 0 8 0 8 min max min max 56 18.31 18.55 .720 .730 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) ordering information ics94201 y flft example: designation for tape and reel packaging lead free, rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device ics xxxx y f lf t
19 ics94201 0428b - 11/28/05 revision history rev. issue date description page # b 11/28/2005 added lf ordering information 18
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us global sites email | print contact idt | investors | press search entire site home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 94201 a dd to m y idt [ ? ] 94201 (desktop chipsets) description 810/810e and solano (815) type chipset market group pc clock additional info the ics94201 belongs to ics new generation of pr ogrammable system clock generators. it employs serial programming i2c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring out put to output skew, chang ing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system bec ome unstable from over clocking. ? 2 - cpus @ 2.5v ? 13 - sdr am @ 3.3v ? 3 - 3v66 @ 3.3v ? 8 - pci @3.3v ? 1 - 24/48mhz@ 3.3v ? 1 - 48mhz @ 3.3v fixed ? 1 - ref @3.3v, 14.318mhz you may also like... related orderable parts attributes 94201df 94201dfl f 94201dflft 94201dft voltage 3.3 v (pv56) 3.3 v (pvg56) 3.3 v (pvg56) 3.3 v (pv56) package ssop 56 ssop 56 ssop 56 ssop 56 speed na na na na temperature c c c c status active active active active sample yes yes no no minimum order quantity 78 78 1000 1000 factory order increment 26 26 1000 1000 related documents type title size revision date datasheet 94201 datasheet 191 kb 11/08/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\94201.mh t
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